Job Summary
NVIDIA is seeking an elite Senior Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world’s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. We’re united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science.
- Minimum Qualification: Degree
- Experience Level: Senior level
- Experience Length: 5 years
Job Description/Requirements
What You Will Be Doing:
- Be responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM.
- Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
- Expected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.
- You will be collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks.
What we need to see:
- B.Tech./ M.Tech or equivalent experience
- 5+ years of relevant experience
- Experience in verification at Unit/Sub-system/SOC level and expertise in Verilog and SystemVerilog
- Expertise in comprehensive verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA)
- Experience in developing and working in functional coverage based constrained random verification environments
- Background in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug